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integrated tft panel power supply with gate modulation and vcom preliminary technical data ADD8733 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features step-up switching regulator with 3 a switch current limit 8 v to 16.5 v input voltage range adjustable output voltage up to 20 v 1.2 a series switch for power sequencing overvoltage protection (ovp) step-down switching regulator with 3 a switch current limit 8 v to 16.5 v input voltage range adjustable output voltage down to 2.5 v gate pulse modulator circuitry independently adjustable delay and falling slope positive charge-pump regulator for vgh negative charge-pump regulator for vgl two vcom amplifiers general power supply sequencing thermal fault protection 650 khz or 1.2 mhz pwm frequency soft start undervoltage lockout (uvlo) 48-lead rohs compliant lfcsp applications tft lcd panels for tvs and monitors block diagram step-down switching regulator two vcom amplifiers control ADD8733 step-up switching regulator and power sequencing gate pulse modulation undervoltage lockout and thermal protection vgl regulator vgh regulator xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x x x x x x x x 05952-001 figure 1. general description the ADD8733 is a 4-channel regulator with two vcom amplifiers and gate pulse modulation (gpm) that provides all the necessary voltages for thin film transistor (tft) liquid crystal displays (lcd). included is a step-up regulator, a step- down regulator for digital logic, two vcom amplifiers, two charge-pump regulators for vgh and vgl, and an integrated gate pulse modulator. by offering a complete power integration solution optimized for tft lcd tvs and monitors, the ADD8733 helps to lower cost, simplify board design, and increase performance over existing solutions. the ADD8733 is offered in a 48-lead rohs compliant lfcsp and is specified over the industrial temperature range of ?40c to +85c.
ADD8733 preliminary technical data rev. pra | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 block diagram .................................................................................. 1 general description ......................................................................... 1 specifications..................................................................................... 3 step-up switching regulator specifications............................. 3 step-down regulator specifications ......................................... 4 positive charge-pump regulator specifications...................... 5 negative charge-pump regulator specifications .................... 5 gate pulse modulator specifications ......................................... 5 vcom amplifier specifications .................................................6 general specifications ..................................................................6 absolute maximum ratings ............................................................7 esd caution...................................................................................7 pin configuration and function descriptions ............................8 timing diagrams............................................................................ 10 typical application circuit ........................................................... 12 land pattern.................................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14
preliminary technical data ADD8733 rev. pra | page 3 of 16 specifications step-up switching regulator specifications v vin = v sd_vin = 12 v, l1= 15 h, t a = 25c, f osc = 650 khz, unless otherwise noted. table 1. parameter symbol conditions min typ max unit supply input voltage vin 8.0 16.5 v maximum duty cycle 70 % output output voltage v su_out vin + 1 20 v load regulation 200 ma i load 800 ma, v su_out = 18 v 1 % line regulation i load = 500 ma, 8 v v sd_vin 16.5 v, v su_out = 18 v 1 % overall regulation line, load, temperature 3 % overvoltage protection v su_d 19.5 20 20.5 v reference fb regulation voltage v su_fb 2.5 v error amplifier transconductance g m 100 a/v error amplifier open-loop voltage gain a vsu 1000 v/v input bias current i b 100 na switch on resistance r ds (on)su 100 m peak current limit i suclset 3 a oscillator oscillator frequency f osc freq = gnd 650 khz freq = vsr_out 1 1200 khz 1 vsr_out pin provides a logic-high output of 5 v.
ADD8733 preliminary technical data rev. pra | page 4 of 16 step-down regulator specifications v vin = v sd_vin = 12 v, l2=10 h, t a = 25c, f osc = 650 khz, unless otherwise noted. table 2. parameter symbol conditions min typ max unit supply input voltage v sd_vin 8.0 16.5 v minimum duty cycle 15 % output output voltage v step_dn 2.5 5 v load regulation 500 ma i load 1000 ma, v step_dn = 3.3 v 1 % line regulation i load = 750 ma, 8 v v sd_vin 16.5 v, v step_dn = 3.3 v 1 % overall regulation line, load, temperature 3 % error amplifer fb regulation voltage v sd_fb 2.5 v fb input bias current i sd_fb tbd na error amplifier open-loop voltage gain a vsd tbd v/v comp output current i sd_comp tbd a switch on resistance r ds (on)sd sd_bs = 5 v, i sd_load = 750 ma 100 m peak current limit i sdclset 3 a oscillator oscillator frequency f osc freq = gnd 650 khz freq = vsr_out 1 1200 khz 1 vsr_out pin provides a logic-high output of 5 v.
preliminary technical data ADD8733 rev. pra | page 5 of 16 positive charge-pump regulator specifications v npcp_sup = 12 v, t a = 25c, f osc = 650 khz, unless otherwise noted. table 3. parameter symbol min typ max unit supply supply voltage v npcp_sup 8 20 v output output current i vgh 50 ma reference fb regulation voltage v npcp_fb 2.5 v negative charge-pump regulator specifications v npcp_sup = 12 v, t a = 25c, f osc = 650 khz, unless otherwise noted. table 4. parameter symbol min typ max unit supply supply voltage v npcp_sup 8 20 v output output voltage v gl (?v npcp_sup + 3) ?2 v output current i vgl 70 ma reference reference voltage v ncp_ref 2.5 v fb regulation voltage v ncp_fb 0 v gate pulse modulator specifications v sd_vin = 12 v, v gpm_h = 28 v, v gpm_l = 12 v 1 , t a = 25c, unless otherwise noted. table 5. parameter symbol conditions min typ max unit input characteristics gpm_h voltage v gpm__h gpm_l + 6 30 v gpm_h input current i gpm__h gpm_flk = gnd, gpm_dpm = logic high tbd s gpm_l voltage v gpm_l 5 gpm_h C 6 v gpm_l input current i gpm_l gpm_flk = gpm_dpm = logic high tbd s control input characteristics gpm_flk voltage low v lowflk 0.8 v gpm_flk voltage high v highflk 2.2 v gpm_flk input current i gpm_flk 0.9 v gpm_flk 3.3 v ?1 +1 a gpm_dpm voltage low v lowdpm 0.8 v gpm_dpm voltage high v highdpm 2.2 v gpm_dpm input current i gpm_dpm 0.9 v v gpm_dpm 3.3 v ?1 +1 a switching characteristics gpm_out discharge current i gpm_out re = 400 , gpm_l = 12 v 30 ma delay characteristics delay time t delay ce = 470 pf tbd s 1 refer to figure 6 in the typica l application circuit section.
ADD8733 preliminary technical data rev. pra | page 6 of 16 vcom amplifier specifications v su_s = 12 v, vcx_pos = 6.0 v, t a = 25c, unless otherwise noted. table 6. parameter symbol conditions min typ max unit input characteristics offset voltage v os tbd mv noninverting input bias current i b 50 300 na input voltage range 2 su_s ? 2 v common-mode rejection ratio cmrr v cm = 2 v to (su_s ? 3) v 60 db output characteristics output voltage swing (high) v oh buffer, i vc_out (source) = 100 a su_s ? 0.08 v output voltage swing (low) v ol buffer, i vc_out (sink) = 100 a 30 mv output current limit i out 250 ma power supply supply voltage v su_s 8 20 v power supply rejection ratio psrr 7.5 v su_s 20.5 v 65 70 db supply current 1 i sy no load, vcx_pos = su_s/2 2 ma 1 supply current for one vcom amplifier. general specifications v vin = v sd_vin = 12 v, t a = 25c, unless otherwise noted. table 7. parameter symbol conditions min typ max unit supply applied input voltage (vin) v vin 8 16.5 v undervoltage lockout rising input voltage (vin) v uvlor tbd 7.5 v falling input voltage (vin) v uvlof 7.2 v thermal protection thermal shutdown rising temperature 145 c thermal shutdown falling temperature 105 c series switch on resistance r ds (on)ssw 200 m peak current i sswpkc tbd ma
preliminary technical data ADD8733 rev. pra | page 7 of 16 absolute maximum ratings table 8. parameter 1 rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tbd sd_vin/sd_sw/sd_bs/sd_fb/sd_comp to su_pgnd ncp_ref/ncp_fb/ncp_drv to npcp_gnd tbd pcp_fb/pcp_drv/npcp_sup to npcp_gnd tbd gpm_flk/gpm_ce/gpm_dpm to gnd tbd gpm_re/gpm_out/gpm_h/gpm_l to gnd tbd tbd vc1_pos/vc1_neg/vc1_ou t/vc2_out/vc2_pos/ vc2_neg to vc1_gnd esd caution su_sw/su_d/su_s/su_fb/su_comp to su_pgnd tbd vgl_dly/su_dly/sd_ss/su_ss/vsr_out to gnd tbd voltage between su_pgnd, npcp_gnd, and gnd 0.5 package power dissipation (p d ) (t j max ? t a )/ ja 25.88c/w thermal resistance for exposed pad soldered to 4-layer jedec pc board ( ja ) maximum junction temperature (t j ) 125c operating temperature range (t a ) ?40c to +85c storage temperature range (t s ) ?65c to +150c reflow peak temperature (20 sec to 40 sec) 250c 1 su_pgnd, vc1_gnd, npcp_gnd, an d gnd are connected to a common ground connection.
ADD8733 preliminary technical data rev. pra | page 8 of 16 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 npcp_sup ncp_drv gnd ncp_fb ncp_ref vgl_dly sd_ss sd_comp sd_fb sd_bs sd_sw sd_sw 48 47 46 45 44 43 42 41 40 39 38 37 vc1_neg vc1_gnd vc2_out vc2_pos vc2_neg su_s su_s su_fb su_d su_d su_sw su_sw 1 2 3 4 5 6 7 8 9 10 11 12 vc1_pos vc1_out gpm_l gpm_ce gpm_flk gpm_dpm gpm_re gpm_out gpm_h pcp_fb npcp_gnd pcp_drv su_pgnd gnd sd_en su_en su_comp su_ss su_dly freq vsr_out sd_vin sd_vin 35 su_pgnd 36 34 33 32 31 30 29 28 27 26 25 pin 1 indicator 05952-002 ADD8733 top view (not to scale) figure 2. pin configuration table 9. pin function descriptions pin o. neonic function description 1 vc1_pos input vcom amplifier 1 positive input 2 vc1_out output vcom amplifier 1 output 3 gpm_l low level voltage for gate pulse modulation 4 gpm_ce capacitor programmable flk to falling slope delay 5 gpm_flk input control pin for gate pulse modulation 6 gpm_dpm input control pin for gate pulse modulation (on/off ) 7 gpm_re resistor programmable gate pulse modulation falling slope 8 gpm_out power out v gh /gate pulse modulation output 9 gpm_h power in high level voltage for gate pulse modulation 10 pcp_fb input positive charge pump feedback 11 npcp_gnd gnd positive and negative charge pump ground 12 pcp_drv positive charge pump capacitor drive 13 npcp_sup power in positive and negative charge pump power in 14 ncp_drv negative charge pump capacitor drive 15 gnd gnd voltage subregulator ground pin 16 ncp_fb input negative charge pump feedback 17 ncp_ref negative charge pump reference 18 vgl_dly delay for step-down 19 sd_ss soft start for step-down 20 sd_comp step-down regulator compensation 21 sd_fb input step-down regulator feedback 22 sd_bs input step-down regulator bootstrap driver power input 23, 24 sd_sw step-down regulator switch node 25, 26 sd_vin power in power vin for step-down regulator's high side switch 27 vsr_out voltage subregulator output voltage 28 freq frequency select 29 su_dly delay for step-up 30 su_ss soft start for step-up 31 su_comp step-up regulator compensation
preliminary technical data ADD8733 rev. pra | page 9 of 16 pin no. mnemonic function description 32 su_en step-up enable for power supply sequencing 33 sd_en step-down enable for power supply sequencing 34 gnd gnd ground pin 35, 36 su_pgnd gnd ground pin for step-up 37, 38 su_sw step-up regulator switch node 39, 40 su_d power in power in for step-up regulator power supply sequencing switch 41 su_fb input step-up regulator feedback 42, 43 su_s power out output from step-up regulator power supply sequencing switch 44 vc2_neg input vcom amplifier 2 negative input 45 vc2_pos input vcom amplifier 2 positive input 46 vc2_out output vcom amplifier 2 output 47 vc1_gnd gnd ground pin for vcom amplifier 1 48 vc1_neg input vcom amplifier 1 negative input
ADD8733 preliminary technical data rev. pra | page 10 of 16 timing diagrams t 1 t 2 delay controlled by gpm_ce t 2 t 1 slope controlled by gpm_re and v gmp_l gnd gnd gnd gpm_dpm gpm_flk gpm_out gmp_h gmp_l 05952-003 figure 3. timing diagram for gate pulse modulator
preliminary technical data ADD8733 rev. pra | page 11 of 16 su_dly su_out sd_out vgl vgl_dly su_en sd_en su_out sd_out, vgl gpm_out gpm_dpm gpm_flk 05952-004 figure 4. timing diagram for power-up sequence 1 su_dly su_out step_dn vgl vgl_dly su_en sd_en su_out step_dn, vgl gpm_out gpm_dpm gpm_flk 05952-005 (high) figure 5. timing diagram for power-up sequence 2
ADD8733 preliminary technical data rev. pra | page 12 of 16 typical application circuit npcp_sup ncp_ref ncp_fb ncp_drv npcp_gnd vc1_gnd vc2_pos vc1_pos vc1_neg vc1_out vc2_neg vc2_out freq vsr_out sd_bs sd_sw sd_sw sd_fb sd_comp sd_vin sd_vin su_sw su_sw su_pgnd su_pgnd su_d su_d su_comp su_s su_s su_fb gpm_l gpm_h pcp_fb pcp_drv gpm_flk gpm_dpm gpm_out gpm_ce gpm_re sd_en su_en gnd gnd c26 r18 d4 c11 r17 r11 c16 c40 pot2 c39 r36 r34 pot1 r2 r27 r23 r29 vcom1_neg vcom1_out vcom2_neg vcom2_out r35 r33 su_out vgl c27, c41 r28 r37 d3 c10 l2 d2 vin 1 c37 r8 r6 r4 c22, c23, c24, c25 step_dn c20 c21 r20 vgl_dly c18 c19 c29 c30 sd_ss su_dly su_ss c5 l1 15h c1, c2, c3, c4 vin vin 1 f1 d1 sk33a-tp c6, c7, c8 r24 c38 c32 r31 c31 c33, c34, c35 su_out r26 r25 jp4 r30 r32 r9 r10 c12 d5 c9 gmp_h su_out su_d gpm_flk r13 c42 gpm_dpm gpm_out c28 c15 r7 r3 sd_en r14 su_en c14 c13 ADD8733 05952-006 vin 1 r21 r16 figure 6. typical application circuit with component variables, 650 khz
preliminary technical data ADD8733 rev. pra | page 13 of 16 land pattern 7.31mm 5.40mm heat sink s older paste are a 1.90mm 5.93mm 1.60mm 0.5mm 0.33mm diameter thermal via 0.075mm 0.28mm 0.075mm 0.69mm 1.60mm 5.78mm 05952-007 figure 7. 48-lead lfcsp (cp-48-1) land pattern
ADD8733 preliminary technical data rev. pra | page 14 of 16 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicato r coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 figure 8. 48-lead lead frame chip scale package [lfcsp] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model temperature range package description package option ADD8733acpz-reel ?40c to +85c 48-lead lfcsp cp-48-1 1 1 z = rohs compliant part.
preliminary technical data ADD8733 rev. pra | page 15 of 16 notes
ADD8733 preliminary technical data rev. pra | page 16 of 16 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr05952-0- 4 /07(pra)

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